1. Field of the Invention
The present invention relates to a memory interface control circuit and, more specifically, to a memory interface control circuit suitable for use in a memory controller which reads data from a double-data-rate SDRAM such as a DDR2-SDRAM (Double Data Rate 2-Synchronous Random Access Memory).
2. Description of the Related Art
Double-data-rate SDRAMs, such as DDR-SDRAM and DDR2-SDRAM, which read/write data at a timing of both rising and falling edges of a clock pulse have become the mainstream of DRAMs. In DDR-SDRAM and DDR2-SDRAM, a data strobe signal DQS is switched to a high impedance state upon elapse of a low-fix time (tRPST: Read-Postamble Period) which occurs at the time insant when RAM read is finished. As has been known, at the time of switching to this high impedance state, gridge noise is generated in the data strobe signal. Since the DDR-SDRAM uses a relatively low transfer frequency, timing to pick up data from a first-in first-out (FIFO) circuit which temporarily latches read data still exists even if gridge noise is generated on the data strobe signal. In the DDR2-SDRAM, however, the transfer frequency is about twice as high as that of the DDR-SDRAM. Therefore, gridge noise mixed in the data strobe signal may result in damage of data stored in the FIFO circuit in some cases. This leads to the problem of difficulties in setting the timing of synchronizing the read data stored in the FIFO circuit. FIG. 6 depicts this situation in the form of a timing chart. In FIG. 6, the gridge noise generated in the data strobe signal DQS1 at the end of the low-fix period destroys the data in the FIFO circuits, as shown at the timing specified by a dotted mark. This timing chart shows that, with respect to the data read from RAMs at both the proximal end and distal end as viewed form a memory controller, the data in the FIFO circuits are destroyed due to the gridge noise which is generated after elapse of the low-fix period tRPST.
In order that the FIFO circuit provide timing of synchroniizing the data, the destruction of data has to be prevented by masking the data strobe signal DQS1 when the data strobe signal DQS1 shifts to a high impedance state. In conventional techniques, the timing of generating a mask-release signal to release the mask applied to the data strobe signal DQS1 is determined by desk calculations. However, in a semiconductor device having a plurality of DDR2-SDRAMs, the time length required for reading data varies depending on differences in the distance from the memory controller, resulting in destruction of some data if the mask-release signal is generated at a specific timing. That is, the timing to generate the release signal is difficult to determine. For example, JP-2001-189078A describes the technique for determining the timing of masking the data strobe signal.
The assigner of the present application proposed, in an earlier application, JP-2004-092268, a memory interface control circuit which generates a secondary data strobe signal by removing gridge noise from a delayed data strobe signal generated by delaying the data strobe signal.
FIG. 7 shows the configuration of the memory interface control circuit described in the earlier application. In the memory interface control circuit, a control circuit 45 has a function of generating a basic mask signal SDE before a delay adjustment, and a function of controlling the delay time of variable delay circuits 3 and 44, thereby allowing a calibration mask signal to be generated at a variable timing. Upon initialiing DDR2-SDRAMs, the control circuit 45 allows the calibration mask signal to be generated by changing the delay time of the variable delay circuit 3. Based on the thus generated data strobe signal which defines the mask timing and the mask release timing, the control circuit 45 allows the data to be read from the DDR2-SDRAMs, whereby the read data is output from a F/F gate 12. A PASS/FAIL determination to specify whether or not the acquired read data is acceptable is carried out to determine an optimum mask timing. For the subsequent read operation, the data strobe signal having the thus determined mask timing is used.
In the configuration of the earlier application, the PASS/FAIL determination is made for the calibration signal based on the actual read data. Therefore, a superior data strobe signal having an optimum mask timing can be obtained. However, the configuration of the control circuit 45 is complicated, and the calibration needs to be carried out at any time during the initialization, resulting in a complex processing.